In high speed line printers print hammer checking arrangements commonly use feedback or echo signals from hammer operating circuits. These are compared one-on-one with activating or selection signals of the hammer operating signals. Since hammer selection and hammer firing occur in advance of the generation of the echo signals a certain amount of overlap is required to print at higher operating speeds. To permit overlap, the hammer selection and echo signals are first stored in separate memories and their contents compared for checking at a later time in the printing cycle. In some cases the generation of echo signals of a later subcycle overlaps the checking of the echo signals of a preceding subcycle. The following U.S. patents are representative of the prior art: Nos. 3,066,601, issued Dec. 4, 1962 to Harold E. Eden; 3,246,292, issued Apr. 12, 1966 to W. D. Woo; 3,140,470, issued July 7, 1964 to A. J. Deerfield; 3,222,651, issued Dec. 7, 1965 to E. S. Fabiszewski, et al; 3,560,926, issued Feb. 2, 1971 to J. Mrkvicka; 3,240,920, issued Mar. 15, 1966 to C. J. Barbagallo, et al.
U.S. Pat. No. 3,474,956, issued Oct. 28, 1969 to P. A. Cain describes a punch machine or drum printer which uses parity checking. A punch selection parity signal generated concurrently with the punch electromagnet selection is stored in a time delay circuit for later comparison with a timed punch operation parity signal occurring later in the operating cycle. The use of memory in timing of punch cycle operations allows punch selection to overlap the parity checking, each punching operation being checked separately.
U.S. Pat. No. 4,008,389, issued Feb. 15, 1977 to J. Brunin, et al, describes a print hammer error checking arrangement for a belt printer in which characters and hammers are aligned in subcycles or subscans. Error detectors are combined with the hammer amplifier circuits which operate the print hammers. In the event the selected amplifier circuit fails to operate, an error signal is generated which is gated through an error detection matrix to an error register which records the number of the column and the number of the subcycle in which the error occurred. Flipflops are set when an error is gated through the matrix and are then checked at the end of printing a line.
In general, the prior art arrangements whether using one-for-one or parity checking has involved relatively complex memory, memory control and other circuitry that require excessive processing time. Such arrangements when adapted to belt printers operating on the subscan principle become even more complex which increases cost and unnecessarily limits the printing rates of the printer mechanism.